求高手帮忙EDA的VHDL编程题，谢谢。

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图画得不错，应该是2路选择器吧
VHDL见下，请笑纳
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY VHDL1 IS
PORT( S: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Y0,Y1,Y2,Y3: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
A: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE AB OF VHDL1 IS
BEGIN
PROCESS(S)
BEGIN
case s is
when "00" => A <= Y0;
when "01" => A <= Y1;
when "10" => A <= Y2;
when "11" => A <= Y3;
when others => NULL;
end case;
END PROCESS;
END ARCHITECTURE ;

至少要实现良以上的，求哪位高手帮帮忙！不要在百度搜的，那样我自己也会课程设计内容与要求 1，用开关按键表示脉冲，每个脉冲代表100米，10个脉冲1