请高人指点下这个VHDL程序

我来说说：--JFQ.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JFQ IS
PORT(RST:IN STD_LOGIC;
ADD:IN STD_LOGIC;
CHOS:IN STD_LOGIC_VECTOR(3 DOWNTO 0);----计分的位选，就是当为0001时用AA1和AA2计，为0010时用BB1和BB2计，以此类推
AA2,AA1,AA0,BB2,BB1,BB0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);---计分的输出--
CC2,CC1,CC0,DD2,DD1,DD0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));---计分的输出--

END ENTITY JFQ ;
ARCHITECTURE ART OF JFQ IS
BEGIN
PROCESS(RST,ADD,CHOS) IS
VARIABLE POINTS_A2,POINTS_A1:STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE POINTS_B2,POINTS_B1:STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE POINTS_C2,POINTS_C1:STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE POINTS_D2,POINTS_D1:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF (ADD'EVENT AND ADD='1') THEN -----开始计分，上升沿有效-----
IF RST='1' THEN -----计分使能，高电平有效-----
POINTS_A2:="0001"; POINTS_A1:="0000";
POINTS_B2:="0001"; POINTS_B1:="0000";
POINTS_C2:="0001"; POINTS_C1:="0000";
POINTS_D2:="0001"; POINTS_D1:="0000"; ---赋初值--
ELSIF CHOS="0001" THEN
IF POINTS_A1="1001" THEN
POINTS_A1:="0000";
IF POINTS_A2="1001" THEN
POINTS_A2:="0000";
ELSE
POINTS_A2:=POINTS_A2+'1';
END IF;
ELSE
POINTS_A1:=POINTS_A1+'1';
END IF;
ELSIF CHOS="0010" THEN
IF POINTS_B1="1001" THEN
POINTS_B1:="0000";
IF POINTS_B2="1001" THEN
POINTS_B2:="0000";
ELSE
POINTS_B2:=POINTS_B2+'1';
END IF;
ELSE
POINTS_B1:=POINTS_B1+'1';
END IF;
ELSIF CHOS="0100" THEN
IF POINTS_C1="1001" THEN
POINTS_C1:="0000";
IF POINTS_C2="1001" THEN
POINTS_C2:="0000";
ELSE
POINTS_C2:=POINTS_C2+'1';
END IF;
ELSE
POINTS_C1:=POINTS_C1+'1';
END IF;
ELSIF CHOS="1000" THEN
IF POINTS_D1="1001" THEN
POINTS_D1:="0000";
IF POINTS_D2="1001" THEN
POINTS_D2:="0000";
ELSE
POINTS_D2:=POINTS_D2+'1';
END IF;
ELSE
POINTS_D1:=POINTS_D1+'1'; ---以上都是BCD加法-----
END IF;
END IF;
END IF;
AA2<=POINTS_A2; AA1<=POINTS_A1; AA0<="0000";
BB2<=POINTS_B2; BB1<=POINTS_B1; BB0<="0000";
CC2<=POINTS_C2; CC1<=POINTS_C1; CC0<="0000";
DD2<=POINTS_D2; DD1<=POINTS_D1; DD0<="0000"; --输出---
END PROCESS;
END ARCHITECTURE ART;

此段有可能是一个部分的程序，不完整。比如那个计数的可能有32位，而此程序只有四个8位的计数器。关键就在那个计分位选CHOS信号。