关于EDA的频率计设计问题？主要是周期怎么测量？各位高手指点一下。。谢谢

呵呵呵。。。

这个是一个开放性设计性的实验课题啊 。、你不是要测量周期么。。

我做过一个关于显示秒表，测量周期的。。。给你我调试过的程序参考

一下，希望对你有所帮助。。

哥们祝你好运～～～～

1.分频器代码：
将2.5MHz脉冲变成100Hz
library ieee;
use ieee.std_logic_1164.all;
entity div is
port(clr,clk: in bit;q: buffer bit);
end div;
architecture a of div is
signal counter:integer range 0 to 12499;
begin
process(clr,clk)
begin
if (clk='1' and clk'event) then
if clr='1' then
counter<=0;
elsif counter=12499 then
counter<=0;
q<= not q;
else
counter<=counter+1;
end if;
end if;
end process;
end a;
2.十进制计数器代码：
原理为加法计数器，计数十时由cout进位
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count10 is
port(clr,start,clk: in bit;
cout: out bit;
daout: out std_logic_vector(3 downto 0));
end count10;

architecture a of count10 is
signal temp:std_logic_vector(3 downto 0);
begin
process(clk,clr)
begin
if clr='1' then
temp<="0000";
cout<='0';
elsif (clk'event and clk='1') then
if start='1' then
if temp>="1001" then
temp<="0000";
cout<='1';
else
temp<=temp+1;
cout<='0';
end if;
end if;
end if;
daout<=temp;
end process;
end a;
3.六进制计数器代码：
原理为加法计数器，计数六时由cout进位。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;entity c6 is
port(clr,start,clk: in bit;
daout: out std_logic_vector(3 downto 0);
cout: out std_logic);
end c6;architecture a of c6 is
signal temp:std_logic_vector(3 downto 0);
begin
process(clk,clr)
begin
if clr='1' then
temp<="0000";
cout<='0';
elsif (clk'event and clk='1') then
if start='1' then
if temp>="0101" then
temp<="0000";
cout<='1';
else
temp<=temp+1;
cout<='0';
end if;
end if;
end if;
end process;
daout<=temp;
end a;
4.报警器代码：
当记时到一小时时，报警器报警，并响十声。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;entity alarm1 is
port(clk, I:in std_logic;
q:out std_logic);
end alarm1;ARCHITECTURE a OF alarm1 IS signal n:integer range 0 TO 20;
signal q0 :std_logic;
beginprocess(clk)
begin
if(clk='1'and clk'event) then
if i='0' then
q0<='0';
n<=0;
elsif (n<=19 and i='1') then
q0<=not q0;
n<=n+1;
else
q0<='0';
end if;
end if;
end process;
q<=q0;
END a;
5.数据选择和数码管选择模块代码：
其功能是选择个计数端口来的数据，当相应的数据到来时数据选择器选择器数据后输出给数码管，并由数码管显示。
library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_UNSIGNED.all;entity seltime is
port(clr,clk: in bit;
dain0,dain1,dain2,dain3,dain4,dain5: in std_logic_vector(3 downto 0);
sel: out std_logic_vector(2 downto 0);
daout: out std_logic_vector(3 downto 0));
end seltime;architecture a of seltime is
signal temp:integer range 0 to 5;
begin
process(clk)
begin
if (clr='1') then
daout<="0000";
sel<="000";
temp<=0;
elsif (clk='1'and clk'event) then
if temp=5 then temp<=0;
else temp<=temp + 1;
end if;
case temp is
when 0=>sel<="000";daout<=dain0;
when 1=>sel<="001";daout<=dain1;
when 2=>sel<="010";daout<=dain2;
when 3=>sel<="011";daout<=dain3;
when 4=>sel<="100";daout<=dain4;
when 5=>sel<="101";daout<=dain5;
end case;
end if;
end process;
end a;
6.数码管驱动模块代码：
数码管驱动电路，驱动数码管发光。
library ieee;
use ieee.std_logic_1164.all; entity deled is
port(num:in std_logic_vector(3 downto 0);
led:out std_logic_vector(6 downto 0));
end deled ; architecture a of deled is
begin
process(num)
begin
case num is
when"0000"=>led<="0111111";-----------3FH
when"0001"=>led<="0000110";-----------06H
when"0010"=>led<="1011011";-----------5BH
when"0011"=>led<="1001111";-----------4FH
when"0100"=>led<="1100110";-----------66H
when"0101"=>led<="1101101";-----------6DH
when"0110"=>led<="1111101";-----------7DH
when"0111"=>led<="0100111";-----------27H
when"1000"=>led<="1111111";-----------7FH
when"1001"=>led<="1101111";-----------6FH
when others=>led<="0000000";-----------00H
end case;
end process;