基于fpga数字时钟设计的主程序

如果你有兴趣，我把细节都给你

module top(
input clk,
input rst,

output CE,
output SCLK,
inout IO,

output CS,
output AO,
output SCL,
output SDI
);

reg read_ds1302_start;
wire read_ds1302_done;
wire[23:0] read_ds1302_time;
read_ds1302_time U1 (clk,rst,read_ds1302_start,read_ds1302_done,read_ds1302_time,CE,SCLK,IO);

reg write_lcd_start;
wire write_lcd_done;
write_lcd_time U2 (clk,rst,CS,AO,SCL,SDI,write_lcd_start,write_lcd_done,read_ds1302_time);

parameter T100ms = 21'd2_000_000;
reg[20:0] count;
always@(posedge clk,negedge rst)
if(!rst)
count <= 0;
else if(count < T100ms)
count <= count + 21'd1;
else
count <= 0;

reg[1:0] i;
reg[3:0] temp;

always@(posedge clk,negedge rst)
if(!rst)
begin
read_ds1302_start <= 0;
write_lcd_start <= 0;
i <= 0;
end
else
case(i)
2'd0: if(count == T100ms)
begin
read_ds1302_start <= 1;
i <= i + 2'd1;
end

2'd1: begin
read_ds1302_start <= 0;
if(read_ds1302_done)
if(read_ds1302_time[3:0] != temp)
begin
temp <= read_ds1302_time[3:0];
write_lcd_start <= 1;
i <= i + 2'd1;
end
else
i <= 0;
end

2'd2: begin
write_lcd_start <= 0;
if(write_lcd_done)
i <= 0;
end

endcase

endmodule