FPGA，vhdl是做什么用的，能举个例子吗

VHDL是一种硬件描述语言，由美国军方御者开发。FPGA是镇野薯现场可编程逻辑阵列。用VHDL语言描述比如与门非门等电路逻脊神辑，然后编译下载到FPGA上，就实现了描述的功能。

Very-High-Speed Integrated Circuit HardwareDescription Language

硬件描述语言啊。

FPGA是用VHDL或者verilogHDL开发的，一般用来实现逻辑，时销汪序电路。

例如计数器，等等。

十计数器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY count IS
PORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0));
END count;
ARCHITECTURE counter OF count IS
SIGNAL count_int:std_logic_vector(0 to 3);
BEGIN
PROCESS(clk,reset)
BEGIN
WAIT UNTIL rising_edge(clk);
IF reset = '1' THEN
count_int <= (OTHERS => '0');
ELSIF enable = '1' THEN
IF(count_int="1001") THEN
count_int<="0000";

ELSE
count_int <= count_int 1;
--ELSE
-- NULL ;
--IF (count_int="1001") THEN
--count_int<御闭="0000";
END IF;
END IF;
END PROCESS;
count <= count_int;
-- IF (reset='0') then
--q<="0000";
---ELSIF(clk'event and clk='1') THEN
--q<=q 1;
--IF (q<="1001") then
--q<="0000";
---END IF;
--IF (reset<='1')THEN
--q<="00";
--ELSIF
--wait until (clk'event and clk='1');
--WAIT UNTIL (clk'EVENT AND clk = '1');

--WAIT UNTIL (clock'EVENT AND clock = '1');
-- q<=q '1';
--end if;
--count<=q;
-- WAIT UNTIL clock = '1';
--if (clock'event and clock='1')then
--WAIT UNTIL rising_edge(clock);
--clock'event and clock='1';
--count <= 0;
--WAIT UNTIL (clock'EVENT AND clock = '1');
--WAIT riseedge clock = '1';
--if (clock'event and clock='1') then
--WAIT UNTIL rising_edge(clock);
--count <= 1;
--WAIT UNTIL (clock'EVENT AND clock = '1');
--WAIT UNTIL clock = '1'亏拆仔;
--if (clock'event and clock='1')then
--WAIT UNTIL rising_edge(clock);
--count <= 2;
--end if;
--end if;
--end if;
-- END PROCESS;
END counter;