用加法器设计个代码转换电路,将BCD代码的8421吗转换为余3码

library ieee；
use ieee.std_logic_1164.all;
package adder_pkg is
component adder port (
A,B,Cin:in std_logic;
Sum,Cout:out std_logic);
end component ;
end adder_pkg;

library ieee;
use ieee.std_logic_1164.all;

entity adder is
port(A,B,Cin:in std_logic;
Sum,Cout:out std_logic);
end entity adder;

architecture one of adder is
begin
Sum<=A xor B xor Cin;
Cout<=(A and B) or (A and Cin) or (B and Cin);
end architecture one;
library ieee;
use ieee.std_logic_1164.all;
entity adder4b_top is
port(A,B:in std_logic_vector(3 downto 0);
C0:in std_logic;
S:out std_logic_vector(3 downto 0);
C3:out std_logic);
end entity adder4b_top;
use work.adder_pkg.all;
architecture one of adder4b_top is
signal C:std_logic_vector(2 downto 0);
begin
u0: adder port map (A=>A(0),B=>B(0),Cin=>c0,Sum=>S(0),Cout=>C(0));
u1: adder port map (A=>A(1),B=>B(1),Cin=>C(0),Sum=>S(1),Cout=>C(1));
u2: adder port map (A=>A(2),B=>B(2),Cin=>C(1),Sum=>S(2),Cout=>C(2));
u3: adder port map (A=>A(3),B=>B(3),Cin=>C(2),Sum=>S(3),Cout=>C3);
sum<=sum+"0011"
end;