用VHDL语言设计实现一个8421码转换为格雷码的代码转换器代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY B2G IS
GENERIC(n:INTEGER :=4);
PORT(
norm : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
grey : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)
);
END B2G;

ARCHITECTURE behave OF B2G IS

SIGNAL temp_normal : STD_LOGIC_VECTOR(n-1 DOWNTO 0);
SIGNAL temp_grey : STD_LOGIC_VECTOR(n-1 DOWNTO 0);

BEGIN
PROCESS(norm)
BEGIN
temp_normal <= norm;
temp_grey(n-1) <= temp_normal(n-1)
FOR i IN n-2 DOWNTO 0 LOOP
temp_grey(i) <= temp_normal(i+1) xor temp_normal(i);
END LOOP;
grey <= temp_grey;
END PROCESS;
END behave;