状态机 实现对101101的检测 verilog

module seq(input clk, input rst, input i, output o);

reg [0:5] seq;

assign o = seq == 6'b101101 ? 1'b1 : 1'b0;

always @(posedge clk, posedge rst) begin
if(rst) begin
seq <= 6'b0;
end else begin
seq <= {seq, i};
end
end

endmodule

module detect(
input clk,
input rst,
input in,
output out
);
parameter IDLE = 3'd0;
parameter A = 3'd1;
/****************************************/
reg [2:0] crt_state,nxt_state;
reg [5:0]data;
always @(posedge clk or negedge rst)
begin
if(!rst)
crt_state <= IDLE;
else
crt_state <= nxt_state;
end
/****************************************/
always @(*)
begin
case(crt_state)
IDLE: if(data==6'b110100) nxt_state = A;
else nxt_state = IDLE;
A : nxt_state = IDLE;
default: nxt_state = IDLE;
endcase
end
/****************************************/
reg out;
always @(posedge clk or negedge rst)
begin
if(!rst)begin
out <= 1'b0;
data<=6'd0;
end
else case(nxt_state)
IDLE : begin
data <= {data[5:0],in};
out <= 1'b0;
end
A : out <= 1'b1;
default: out <= 1'b0;
endcase
end