VHDL优先编码器，用when...else...

可以用两种方法，when else和if elsif else，，下面分别是两种程序，和仿真的波行图

library ieee;

use ieee.std_logic_1164.all;

entity youxian is

port(input:in std_logic_vector(7 downto 0);

     output:out std_logic_vector(2 downto 0));

end entity;

architecture art of youxian is

begin

 output<="111" when input(7)='1' else

         "110" when input(6)='1' else

         "101" when input(5)='1' else

         "100" when input(4)='1' else

         "011" when input(3)='1' else

         "010" when input(2)='1' else

         "001" when input(1)='1' else

         "000";

end art;

library ieee;

use ieee.std_logic_1164.all;

entity youxian is

port(input:in std_logic_vector(7 downto 0);

     output:out std_logic_vector(2 downto 0));

end entity;

architecture art of youxian is

begin

 process(input)

  begin

   if input(7)='1' then

      output<="111";

   elsif input(6)='1' then

      output<="110";

   elsif input(5)='1' then

      output<="101";

   elsif input(4)='1' then

      output<="100";

   elsif input(3)='1' then

      output<="011";

   elsif input(2)='1' then

      output<="010";

   elsif input(1)='1' then

      output<="001";

   elsif input(0)='1' then

      output<="000";

   else output<="000";

   end if;

 end process;

end art;