用verilog HDL语言写一个分频器,将50MHZ分成1KHZ

求大神帮忙,需要完整的代码
2024-12-29 23:13:23
推荐回答(1个)
回答1:

parameter N = 32'd25000000;
reg [31:0]count;
reg clk_1M;
reg rst;
always@(posedge clk_50M)
begin
if(rst == 1)
begin
clk_1M <= 0;
cout <= 0;
end
else if(count == N)
clk_1M <= ~ clk_1M;
end