【CPLD⼀FPGA】求把“二进制数”转换成“BCD码”的方法（verilog和VHDL均可）

告诉你一个蛮简单的方法哦，确定了要转换的二进制数以后，点击电脑“开始”-“附件”-“计算器”，然后选择科学型。
选择“二进制”，把你需要转换的二进制数填上去，填完以后，再按“十进制”，这个时候二进制数就转换为了十进制数了。这个时候转化成BCD码就轻而易举啦，你知道BCD码就是“8421”权位码，就是“0”至"9"这十个数值的二进码来表示，所以你只需要把十进制数中每位数字用4个BCD二进制码来表示，然后在按照权位依次连起来就可以了。举个例子，十进制数325，3就是0011,2就是0010，5就是0101，连起来就是1100100101。呵呵，原创方法，很实用的哦

先转化为十进制,再转化为BCD码.例:二进制数11011011,转化为十进制数为219.再分别用四位二进制数表示219的个十百位,百位2为:0010;十位1为:0001;个位9为1001.把它们拼起来就可以了.即:二进制数11011011的BCD码是:001000011001.

//电压值BCD转换模块
module BCD(dato,sq1);
input [7:0]dato;
output [11:0]sq1;
reg [11:0]sq1;
reg [7:0] dato1,dato2;
always @(dato)
begin
if(dato>=8'hc8)
begin
dato1=dato-200;
sq1[11:8]=4;
end
else if(dato>=8'h96)
begin
dato1=dato-150;
sq1[11:8]=3;
end
else if(dato>=100)
begin
dato1=dato-100;
sq1[11:8]=2;
end
else if(dato>=50)
begin
dato1=dato-50;
sq1[11:8]=1;
end
else
begin
dato1=dato;
sq1[11:8]=0;
end
end

always @(dato1)
begin
if(dato1>=45)
begin
dato2=dato1-45;
sq1[7:4]=9;
end
else if(dato1>=40)
begin
dato2=dato1-40;
sq1[7:4]=8;
end
else if(dato1>=35)
begin
dato2=dato1-35;
sq1[7:4]=7;
end
else if(dato1>=30)
begin
dato2=dato1-30;
sq1[7:4]=6;
end
else if(dato1>=25)
begin
dato2=dato1-25;
sq1[7:4]=5;
end
else if(dato1>=20)
begin
dato2=dato1-20;
sq1[7:4]=4;
end
else if(dato1>=15)
begin
dato2=dato1-15;
sq1[7:4]=3;
end
else if(dato1>=10)
begin
dato2=dato1-10;
sq1[7:4]=2;
end
else if(dato1>=5)
begin
dato2=dato1-5;
sq1[7:4]=1;
end
else
begin
dato2=dato1;
sq1[7:4]=0;
end
end

always @(dato2)
begin
if(dato2>=4)
sq1[3:0]=8;
else if(dato2>=3)
sq1[3:0]=6;
else if(dato2>=2)
sq1[3:0]=4;
else if(dato2>=1)
sq1[3:0]=2;
else
sq1[3:0]=0;
end

endmodule

译码器就可以

基本思路是把二进制按4位一组分开,把每一组对应的二进制数转换成bcd码表,最后把所有位进行bcd码相加,第一个4位的码表也可以省略,第二个4位对于关系是
4'h0: 10'h000;
4'h1: 10'h016;
4'h2: 10'h032;
4'h3: 10'h048;
4'h4: 10'h064;
4'h5: 10'h080;
4'h6: 10'h096;
4'h7: 10'h112;
4'h8: 10'h128;
4'h9: 10'h144;
4'ha: 10'h160;
4'hb: 10'h176;
4'hc: 10'h192;
4'hd: 10'h208;
4'he: 10'h224;
4'hf: 10'h240;
第3组对于你来说只有3位
4'h0: 14'h0000;
4'h1: 14'h0256;
4'h2: 14'h0512;
4'h3: 14'h0768;
4'h4: 14'h1024;
4'h5: 14'h1280;
4'h6: 14'h1536;
4'h7: 14'h1792;
把11位二进制查表得出的3个数进行bcd码相加
这里把每个结果按同级单个bcd码相加,也就是>9对结果加6,>19对结果加12,>29对结果加18类推,当然高一级的bcd码要加上低一级的进位,也就是高出4位的部分,最后把结果拼接
给你一个16位有符号的例子
module bcd(clk,
hex,
dec);

input clk;
input [16:0] hex;
output [19:0] dec;

wire [15:0] rrhex;
reg [3:0] rhex[3:0];

reg [17:0] rhexd;
reg [13:0] rhexc;
reg [9:0] rhexb;
reg [3:0] rhexa;

reg [5:0] resa,resb,resc,resd;
reg [3:0] rese;

assign rrhex = hex[16] ? ~hex[15:0]+1'b1 : hex[15:0]; //去符号
assign dec = {rese,resd[3:0],resc[3:0],resb[3:0],resa[3:0]};

always@(posedge clk) //第一级寄存器
begin
rhex[3] <= rrhex[15:12];
rhex[2] <= rrhex[11:8];
rhex[1] <= rrhex[7:4];
rhex[0] <= rrhex[3:0];
end

always@(posedge clk) //第二级寄存器,千
begin
case(rhex[3])
4'h0: rhexd <= 18'h00000;
4'h1: rhexd <= 18'h04096;
4'h2: rhexd <= 18'h08192;
4'h3: rhexd <= 18'h12288;
4'h4: rhexd <= 18'h16384;
4'h5: rhexd <= 18'h20480;
4'h6: rhexd <= 18'h24576;
4'h7: rhexd <= 18'h28672;
default: rhexd <= 10'h00000;
endcase
end

always@(posedge clk)
begin
case(rhex[2])
4'h0: rhexc <= 14'h0000;
4'h1: rhexc <= 14'h0256;
4'h2: rhexc <= 14'h0512;
4'h3: rhexc <= 14'h0768;
4'h4: rhexc <= 14'h1024;
4'h5: rhexc <= 14'h1280;
4'h6: rhexc <= 14'h1536;
4'h7: rhexc <= 14'h1792;
4'h8: rhexc <= 14'h2048;
4'h9: rhexc <= 14'h2304;
4'ha: rhexc <= 14'h2560;
4'hb: rhexc <= 14'h2816;
4'hc: rhexc <= 14'h3072;
4'hd: rhexc <= 14'h3328;
4'he: rhexc <= 14'h3584;
4'hf: rhexc <= 14'h3840;
default: rhexc <= 14'h0000;
endcase
end

always@(posedge clk)
begin
case(rhex[1])
4'h0: rhexb <= 10'h000;
4'h1: rhexb <= 10'h016;
4'h2: rhexb <= 10'h032;
4'h3: rhexb <= 10'h048;
4'h4: rhexb <= 10'h064;
4'h5: rhexb <= 10'h080;
4'h6: rhexb <= 10'h096;
4'h7: rhexb <= 10'h112;
4'h8: rhexb <= 10'h128;
4'h9: rhexb <= 10'h144;
4'ha: rhexb <= 10'h160;
4'hb: rhexb <= 10'h176;
4'hc: rhexb <= 10'h192;
4'hd: rhexb <= 10'h208;
4'he: rhexb <= 10'h224;
4'hf: rhexb <= 10'h240;
default: rhexb <= 10'h000;
endcase
end

always@(posedge clk)
begin
rhexa <= rhex[0];
end

always@(posedge clk)
begin
resa = addbcd4(rhexa[3:0],rhexb[3:0],rhexc[3:0], rhexd[3:0]);
resb = addbcd4(resa[5:4], rhexb[7:4],rhexc[7:4], rhexd[7:4]);
resc = addbcd4(resb[5:4], rhexb[9:8],rhexc[11:8], rhexd[11:8]);
resd = addbcd4(resc[5:4], 4'h0, rhexc[13:12],rhexd[15:12]);
rese = resd[5:4] + rhexd[17:16];
end

function [5:0] addbcd4;
input [3:0] add1,add2,add3,add4;
begin
addbcd4 = add1 + add2 + add3 + add4;
if(addbcd4 > 6'h1d) //>29 最低有一个可能出现0xf,但由二进制转换而来的数在这里不会出现大于40的情况
addbcd4 = addbcd4 + 5'h12;
else if(addbcd4 > 5'h13) //>19
addbcd4 = addbcd4 + 4'hc;
else if(addbcd4 > 4'h9) //>9
addbcd4 = addbcd4 + 4'h6;
end
endfunction

endmodule