用VHDL语言设计2位数值比较器 要程序 急！！

优点：逻辑少，关键路径少，布线方便
缺点：书写麻烦
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Comp is
port (
A1 : in std_logic;
B1 : in std_logic;
A0 : in std_logic;
B0 : in std_logic;
AsmallerB : out std_logic;
AgreaterB : out std_logic;
AequalB : out std_logic
);
end Comp;
architecture RTL of Comp is
signal S_TMP : std_logic_vector(3 downto 0);
begin
S_TMP <= A1 & B1 & A0 & B0;
process (S_TMP) begin
case (S_TMP) is
when "0000" => AsmallerB <= '0';AgreaterB <= '0';AequalB <= '1';
when "0001" => AsmallerB <= '1';AgreaterB <= '0';AequalB <= '0';
when "0010" => AsmallerB <= '0';AgreaterB <= '1';AequalB <= '0';
when "0011" => AsmallerB <= '0';AgreaterB <= '0';AequalB <= '1';
when "0100" => AsmallerB <= '1';AgreaterB <= '0';AequalB <= '0';
when "0101" => AsmallerB <= '1';AgreaterB <= '0';AequalB <= '0';
when "0110" => AsmallerB <= '1';AgreaterB <= '0';AequalB <= '0';
when "0111" => AsmallerB <= '1';AgreaterB <= '0';AequalB <= '0';
when "1000" => AsmallerB <= '0';AgreaterB <= '1';AequalB <= '0';
when "1001" => AsmallerB <= '0';AgreaterB <= '1';AequalB <= '0';
when "1010" => AsmallerB <= '0';AgreaterB <= '1';AequalB <= '0';
when "1011" => AsmallerB <= '0';AgreaterB <= '1';AequalB <= '0';
when "1100" => AsmallerB <= '0';AgreaterB <= '0';AequalB <= '1';
when "1101" => AsmallerB <= '1';AgreaterB <= '0';AequalB <= '0';
when "1110" => AsmallerB <= '0';AgreaterB <= '1';AequalB <= '0';
when "1111" => AsmallerB <= '0';AgreaterB <= '0';AequalB <= '1';
when others => AsmallerB <= '0';AgreaterB <= '0';AequalB <= '0';
end case;
end process;
end RTL;