以真值表为依据,用vhdl描述2输入与非门

2025-03-09 09:13:48
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回答1:

ENTITY and_not IS
PORT(in_1,in_2:IN bit;out_0:OUT bit);
END and_not;
architecture one of and_not is
begin
out_0 <= '0' when (in_1 and in_2 ='1') else
'1';
end one;