vhdl 按键控制数码管加一减一

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
PORT (a,b,RST,EN : IN STD_LOGIC;
CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
XOUT : STD_LOGIC_VECTOR(7 DOWNTO 0); );
END CNT10;

ARCHITECTURE behav OF CNT10 IS
PROCESS(a,b, EN) VARIABLE CQI : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN
IF en= '1' THEN ELSIF a'EVENT AND a='1'
THEN
CQI := CQI + 1;
ELSIF b'EVENT AND b='1'
then CQI := CQI -1;
end if；
if CQI<="0000" THEN CQI<="1001";
END if
if CQI<="1001" then CQI<="0000";
end if;

CQ<=CQI;
end Process;
PROCESS (CQ,EN)BEGIN
IF EN = ‘1’ THEN
IF CQ = “0000” THEN XOUT <= “0111111”;
ELSIF CQ = “0001” THEN XOUT <= “0000110”;
ELSIF CQ= “0010” THEN XOUT <= “1011001”;
ELSIF CQ = “0011” THEN XOUT <= “1001111”;
ELSIF CQ= “0100” THEN XOUT <= “1100110”;
ELSIF CQ= “0101” THEN XOUT <= “1101101”;
ELSIF CQ= “0110” THEN XOUT <= “1111101”;
ELSIF CQ= “0111” THEN XOUT <= “0000111”;
ELSIF CQ= “1000” THEN XOUT <= “1111111”;
ELSIF CQ= “0110” THEN XOUT <= “1101111”;
END IF;
END PROCESS;
END behav ;